ADC Module
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| An analog-to-digital converter (ADC) converts an analog signal into an equivalent digital number. PIC 16C74A has an inbuilt ADC with the following features - |
- 8-bit conversion
- 8 analog input channels
- An analog multiplexer
- A sample and hold circuit for signal on the selected input channel
- Alternative clock sources for carrying out conversion
- Adjustable sampling rate
- Choice of an internal or external reference voltage
- Interrupt to microcontroller on end of conversion
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| Port A and Port E pins are used for analog inputs/reference voltage for ADC. In A/D conversion, the input analog voltage is digitized and an equivalent digital output is generated as shown in the figure. |
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Fig 23.1 Digital output versus analog input
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Port-A pins (Alternate functions)
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RA0/AN0 - can be used as analog input-0
RA1/AN1 - can be used as analog input-1
RA2/AN2 - can be used as analog input-2
RA3/AN3/Vref - can be used as analog input-3 or analog reference voltage
RA4/TOCKI - clock input to Timer-0
RA5/ /AN4 - can be used for analog input 4 or slave select for the synchronized serial port.
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| Port-E pins (Alternate functions) |
RE0/  /AN5 - can be used as analog input-5
RE1/  /AN6 - can be used as analog input-6
RE2/  /AN7 - can be used as analog input-7
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| PIC microcontroller has internal sample and hold circuit. The input signal should be stable across the capacitor before the conversion is initiated. |
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Fig 23.2 Sample and Hold Circuit
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| After waiting for the sampling time, a conversion can be initiated. The ADC Circuit will open the sampling switch and carry out the conversion of the input voltage as it was at the moment of opening of the switch. Upon completion of the conversion, the sampling switch is again closed and VHold once again tracks VSource. |
| Using the A/D Converter |
| Registers ADCON1, TRISA, and TRISE must be initialized to select the reference voltage and input channels. The first step selects the ADC clock from among the four choices (fosc/2, fosc/8, fosc/32, and RC). The constraint for selcting clock frequency is that the ADC clock period must be 1.6micro seconds or greater. |
| The A/D module has 3registers. These registers are:- |
- A/D result register (ADRES)
- A/D control register 0 (ADCON 0)
- A/D control register 1 (ADCON 1)
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| The ADCON0 register, which is shown below, controls the operation of A/D module. |
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Fig 23.3 ADCON0 register
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Bit 7-6 - A/D Clock select bits
ADCS1:ADCS0 |
00 = fosc/2
01 = fosc/8
10 = fosc/32
11 = fRC- clock derived from an internal RC oscillator
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Bit 5-3 - A/D Channel Select
CHS2:CHS0 |
000 - Channel 0 - AN0
001 - Channel 1 - AN1
010 - Channel 2 - AN2
011 - Channel 3 - AN3
100 - Channel 4 - AN4
101 - Channel 5 - AN5
110 - Channel 6 - AN6
111 - Channel 7 - AN7
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| Bit 2 - A/D conversion status bit |
GO / 
if A/D Converter is enabled (ie. ADON = 1) then
If GO /  = 1, A/D conversion is in progress
(setting this bit starts A/D conversion)
If GO /  = 0, A/D conversion is not in progress
(This bit is automatically cleared by hardware when A/D conversion is complete) |
| Bit1 - Unimplemented |
| Bit 0 - ADON: A/D On bit |
- A/D Converter module is ON
- A/D Converter module is OFF
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| ADCON1 Register |
| This register specifies the analog inputs |
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Fig 23.4 ADCON1 register
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PCFG2:PCFG0
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RA0
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RA1
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RA2
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RA5
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RA3
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RE0
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RE1
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RE2
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VREF
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000
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A
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A
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A
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A
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A
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A
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A
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A
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VDD
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001
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A
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A
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A
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A
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VREF
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A
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A
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A
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RA3
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010
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A
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A
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A
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A
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A
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D
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D
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D
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VDD
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011
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A
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A
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A
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A
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VREF
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D
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D
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D
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RA3
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100
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A
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A
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D
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D
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A
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D
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D
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D
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VDD
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101
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A
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A
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D
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D
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VREF
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D
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D
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D
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RA3
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11X
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D
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D
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D
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D
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D
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D
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D
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D
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-
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Fig 23.5 PCFG2:PCFG0 = A/D Port configuration control bits
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A = Analog input
D = Digital I/O |
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Fig 23.6 Schematic diagram of A/D convertor analog inputs and reference voltage
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| Steps for A/D conversion |
- Configure A/D module
- Configure analog inputs/voltage reference and digital I/O (ADCON1)
- Select A/D Channel (ADCON0)
- Select A/D Conversion Clock (ADCON0)
- Turn on A/D Module (ADCON0)
- Configure A/D Interrupt (Optional)
- Clear ADIF bit in PIR1 register
- Set ADIE bit in PIE1 register
- Set GIE bit
- Wait for required acquisition time
- Start Conversion - set GO/
 bit (ADCON0)
- Wait for A/D conversion to complete, by either polling GO/
 bit or by waiting for the A/D interrupt
- Read A/D result registers (ADRES). Clear ADIF if required.
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Example Program
A/D conversion with interrupt |
org 000H
goto Mainline
org 020H
bsf STATUS, RP0 ; Select Bank 1
clrf ADCON 1 ; Configure A/D inputs
bsf PIE1, ADIE ; Enable A/D interrupt
bcf STATUS, RP0 ; Select Bank 0
movlw 081H ; Select fosc/32, channel 0, A/D on
movwf ADCON0
bcf PIR1, ADIF
bsf INTCON, PEIE ; Enable peripheral and global interrupt bits
bsf INTCON, GIE ; interrupt bits
; Ensure that the required sampling time of the selected input channel has been elapsed.
; Then conversion may be started.
; bsf ADCON0, GO ; Start A/D conversion.
; ADIF bit will be set and GO/ 
; bit is cleared upon completion of A/D conversion.
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Interrupt Service Routine
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Org 004H
Movf ADRES, W ; Result of A/D conversion in W
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| Consideration of Sampling Time |
When a channel is selected (writing to ADCON0), the switch 'SW' in Fig 23.8 is closed, changing CHOLD to VSource . When A/D conversion is started (setting Go bit in ADCON0), SW is opened. The time from the closure of 'SW' till the voltage across CHOLD (Vo) reaches VSource is the minimum sampling time Ts . The actual sampling time can be higher than Ts .
The graph between Ts and source resistance RSource is shown in Fig 23.7.+ |
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Fig 23.7 Relation between sampling time and source resistance
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Fig 23.8 Sampling circuit in the PIC µC
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Rss is the resistance of the sampling switch 'SW' and CHold is the charge holding capacitance. CHold is nearly 50pF. RSource is the impedance of the external analog source Vsource. Once the switch 'SW' is closed, the capacitor Chold takes some time to charge up. This time it is called the sampling time (Ts). This time varies linearly with RSource as shown. The recommended value of impedance of the external analog source, Vsource, is less than 10kΩ.
The circuit in Fig 23.8 is a first order RC circuit. When SW is closed, Vo varies as shown in Fig 23.9. |
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Fig 23.9
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From Fig 23.9,
Ts = 5  = 5 ( Rsource + Rss) CHOLD
= 5 Rss CHOLD + 5 Rsource CHOLD |
| Hence sampling time Ts varies linearly with RSource as shown in Fig 23.7. |
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