Lecture 22 : CCP Modules

Capture / Compare /PWM (CCP) Modules: PIC16C74A has two CCP Modules. Each CCP module contains a 16 bit register (two 8-bit registers) and can operate in one of the three modes, viz., 16-bit capture, 16-bit compare, or up to 10-bit Pulse Width Modulation (PWM). The details of the two modules (CCP1 and CCp2) are given as follows. CCP1 Module: CCP1 Module consists of two 8-bit registers, viz., CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1 Module. CCP2 Module: CCP2 Module consists of two 8 bit registers, viz., CCPR2L (Low byte) and CCPR2H (high byte). The CCP1CON register controls the operation of CCP2 Module. Both CCP1 and CCP2 modules are identical in operation with the exception of the operation of special event trigger. The following table shows the timer resources for the CCP Mode. CCP Mode Timer Used Capture Compare PWM Timer 1 Timer 1 Timer 2 CCP1CON Register (Address 17H ) CCP2CON Register is exactly similar to CCP1CON register. CCP2CON Register address is 1DH. CCP1CON controls CCP module1 where as CCP2CON controls CCP Module2. Bit 5-4:        CCP1X CCP1Y: PWM least significant bits. These bits are of no use in Capture mode. In PWM Mode, these bits are the two Lsbs of the PWM duty cycle. The eight Msbs are found in CCPR1L. Thus the PWM mode operates in 10-bit mode. Bit 3-0: CCP1M3:CCP1MO (CCP1 Mode select bits) 0000=Capture/Compare/PWM Mode off 0100=Capture mode, every falling edge 0101=Capture mode, every rising edge 0110=Capture mode, every 4 th rising edge 0111=Capture mode, every 16 th rising edge 1000=Compare mode, set output on match (CCP1IF bit is set) 1001=Compare mode, clear output on match (CCP1IF bit is set) 1010=Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin unaffected) 1011=Compare mode, trigger special event (CCP1IF bit is set;CCP1 resets Tmr1; CCP2 resets TMR1 and starts A/D conversion if A/D module is Enabled) 11XX=PWM mode. Capture Mode (CCP1): Capture Mode captures the 16-bit value of TMR1 into CCPR1H:CCPR1L register pair in response to an event occurring on RC2/CCP1 pin. Capture Mode for CCP2 is exactly similar to that of CCP1. An event on RC2/CCP1 pin is defined as follows: Every falling edge Every rising edge. Every 4 th rising edge. Every 16 th rising edge. As mentioned earlier, this event is decided by bit 3-0 of CCP1CON register. Schematic diagram for capture mode of operation Fig 22.1  Capture operation Required condition for capture mode: RC2/CCP1 pin should be configured as an input by setting TRISC (bit 2). Timer 1 should be operated from the internal clock (fosc/4), i.e., timer mode or in synchronized counter mode. Compare Mode (CCP1) Compare mode for CCP2 is similar to that of CCP1, except that in special event trigger mode, CCP1 resets TMR1 only, whereas CCP2 resets TMR1 and starts A/D conversion if A/D module is enabled. In compare mode, the 16-bit CCPR1 register value is compared against TMR1 register pair (TMR1H and TMR1L) value. When a match occurs, the RC2/CCP1 pin is driven high or driven low or remains unchanged as decided by CCP1CON<3:0> bits. Fig 22.2   Compare Operation Required conditions for compare mode RC2/CCP1 pin must be configured as an output by clearing TRISC<2> bit. Timer-1 should be operated in timer mode (i.e., internal clock source of  fosc/4)  or in synchronized counter mode. In software interrupt mode, CCP1IF bit is set but CCP1 pin in unaffected. As shown in the figure, in special event trigger mode, both CCP1 and CCP2 intiates an A/D conversion. PWM mode (CCP1) Both CCP1 and CCP2 have similar operation in PWM mode. Here we will discuss PWM with respect to CCP1. In PWM mode, the CCP1 pin produces upto a 10-bit resolution Pulse Width Modulation (PWM)  output. RC2/CCP1 pin should be configured in the uotput mode by clearing TRISC<2>  bit. The schematic block diagram of CCP1 module in PWM mode is shown in the figure. Fig 22.3   PWM Operation It can be noted that PR2 (Period Register, 8 bit)  decides the PWM period where CCPR1L (8-bits)  and CCP1CON <5:4> (2-bits)  decide the PWM duty cycle. When TMR2 equals PR2, the SR latch is set and RC2/CCP1 pin is pulled high. In the same time, TMR2 is cleared and the duty cycle value available in CCPR1L is latched to CCPR1H. CCPR1H, CCP1CON <5:4>  decide the duty cycle and when this 10-bit ewquals the TMR2+2 prescaler or Q-bits, the SR latch is set and RC2/CCP1 pin is driven low. A PWM output as shown has a time period. The time for which the output stays high is called duty cycle. PWM Period The PWM period is specified by writing to PR2 register. The PWM period can be calculated using the following formula: PWM period = [( PR 2) + 1] × 4 × T osc × (TMR2 prescale value) PWM frequency = 1/ PWM period When TMR2 is equal to PR2, the following events occur on the next increment cycle. TMR2 is cleared the CCP1 pin is set (if PWM duty cycle is 0 The PWM duty cycle is latched from CCPR1L into CCPR1H PWM duty cycle The PWM duty cycle is specified by writing to the CCPR1L register and to CCP1CON < 5 : 4 > bits. Up to 10-bit resolution is available where CCPR1L contains the eight MSBs and CCP1CON < 5 : 4 > contains the two LSB's. The 10-bit value is represented by CCPR1L : CCP1CON < 5 : 4 >. The PWM duty cycle is given by PWM duty cycle = (CCPR1L : CCP1CON < 5 : 4 > ). T osc . (TMR2 prescale value) To understand the 10-bit counter configuration from Timer-2, let us first see the counting mechanism of Timer-2,  as shown in Fig 22.4.  Fig 22.4  Counting mechanism  in Timer - 2 If the prescaler is 1, the 10-bit counter is configured as follows Fig 22.5  Prescaler set to divide by one If the prescaler is 4, the 10-bit counter is configured as follows. Fig 22.6  Prescaler programed to divide by four If the prescaler is 16, the 10-bit counter is realized as follows. Fig 22.7  Prescaler programed to divide by 16 Although CCPR1L and CCP1CON < 5 : 4 > can be written to at anytime, the duty cycle value is not latched into CCPR1H until a match between PR2 and TMR2 occurs. In PWM mode, CCPR1H is a read-only register. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2-bits of prescaler, the CCP1 pin is cleared. Maximum PWM resolution (bits) for a given PWM frequency can be calculated as If the PWM duty cycle is longer than the PWM period, then the CCP1 pin will not be cleared. PWM Period and duty cycle calculation Example: Desired PWM frequency  =  78.125 kHz f osc = 20MHz TMR2 Prescalar = 1 Find the maximum resolution of duty cycle that can be used with a 78.124 kHz frequency and 20 MHz oscillator.   256 =  2PWM Resolution At most, an 8-bit resolution duty cycle can be obtained from a 78.125 kHz frequency and 20 MHz oscillator ie, 0 CCPR1L : CCP1CON <5 : 4>  ≤ 255 . Any value greater than 255 will result in a 100 % duty cycle. The following table gives the PWM frequency fPWM if fosc = 20MHz Duty cycle resolution 10-Bit counter scale PR2 value Prescaler 1 Prescaler 4 Prescaler 16 10 bit 1024 255 19.53 KHz 4.88 kHz 1.22 kHz ≈ 10 bit 1000 249 20kHz 5kHz 1.25kHz 8 bit 256 63 78.125kHz 19.53kHz 4.88kHz 6 bit 64 15 312.5kHz 78.125kHz 19.53kHz