Lecture 36 : PowerPC Architecture

In February 1990, IBM introduced RS/6000 microprocessor based on POWER architecture with UNIX operating system. PowerPC was second generation POWER architecture. It has Reduced Instruction Set Computer (RISC) architecture. RISC architecture tries to keep the processor as busy as possible. Salient features of RISC architecture are -

Fixed length instructions (4 byte instructions). This allows single decoding mechanism Mostly single cycle instruction execution Less number of instructions

PowerPC was created in 1991 by Apple-IBM-Motorola alliance. Originally intended for personal computers , PowerPC CPUs have since become popular embedded and high-performance processors as well. It is largely based and compatible with POWER microprocessor. Design features of PowerPC are as follows -

Broad range implementation Simple processor design Superscalar architecture Multiprocessor features 64-bit architecture Support for operation in both big-endian and little-endian mode. PowerPC can switch from one mode to another at run time. Separate set of floating point instructions for Separate set of Floating Point Registers (FPRs) for floating-point instructions

Motorola PowerPC 601 was the first PowerPC. Few of its features were -

64-bit microprocessor 32-bit address lines Can handle integer data of 8, 16 and 32 bits RISC architecture with 4 byte instruction length PC 601 has virtual memory addressing of 4 penta byte.

Apart from the changes to the instruction set, the most significant changes in PowerPC were in the memory model and the memory management definition. In the POWER Architecture, the processor did not maintain data memory consistent with either I/O accesses or instruction fetches. Software had to manage memory consistency for both these areas. Before copying an area of memory to disk, software had to ensure that any modified copies of the memory area that were in the data cache had been written to main memory. Before starting a read from disk, software had to ensure that the data cache did not contain a copy of any part of the memory area, and software had to invalidate any copy of the memory area in the instruction cache before restarting the program that requested the operation. POWER processors always accessed main memory through the caches.

PowerPC memory model, however, provides greater flexibility. It implements processor-enforced data memory consistency, relieving software of the responsibility for the consistency of memory with respect to I/O operations. The model allows speculative access to any page unless it has an attribute indicating that it contains I/O or it exhibits other volatile characteristics. It also makes it possible to map I/O into the main memory space.

As in the POWER memory model, the PowerPC memory model requires software to maintain instruction memory consistent with data memory. Programs that modify or generate instructions must ensure that cached copies of a memory area containing the new instructions are consistent with the main memory before attempting to execute those instructions.

Fig 36.1   Branch Processing Unit of PowerPC

The Branch Processing Unit (BPU) looks at lower four instructions in instruction queue to bring the branch instruction in advance. The jump instruction is analyzed and the next instruction is brought and executed till the write-back stage. With this the branch takes single cycle. A branch instruction has a Jump Prediction Bit associated with which tells whether there is likelihood of jump or not. In case a jump is predicted new instructions may be brought in for the entire instruction queue. Later, if the prediction comes out to be true then the execution continues normally and we have considerable amount of performance gain. However, if branch prediction turns out to be false then we have something called Branch Folding. In branch folding all instructions executed after the prediction are discarded and the execution resumes just after branch instruction. We have loss of instruction cycles in this case.

The PowerPC Architecture permits a range of implementations from low-cost controllers through high-performance processors. It allows the implementation of processors targeted for desktop and notebook systems, yet it contains features to support the efficient implementation of processors for use in a range of multiprocessor systems.