Lecture 34 : Use of Translation Look-aside Buffer (TLB) in 80386

Use of Translation Look-aside Buffer (TLB) in 80386 It is cumbersome and time consuming to calculate the physical address from linear address for every memory location. A Translation Look-aside Buffer (TLB) simplifies the process. TLB is a page table cache, which stores the 32 recently accessed page table entries. The paging unit receives a 32-bit linear address from the segmentation unit. The upper 20 bits of the linear address is compared with all 32-entries in the translation look-aside buffer (TLB) to check if it matches with any of the entries. If it matches, the 32-bit physical address is calculated from matching TLB entry and placed on the address bus. Fig. 34.1  TLB organization in 80386 Structure of TLB: TLB has 4 sets of eight entries each. Each entry consists of a TAG and a DATA. Tags are 24 bit wide. They contain 20 upper bits of linear address, a valid bit and three attribute bits. The Data portion of each entry contains higher 20 bits of the Physical address. Fig.  34.2  Structure of TLB Introduction to Intel 80486: CPU 80486 DX from Intel is the first 32-bit microprocessor to have an inbuilt floating point unit. It retained the complex instruction set of 80386 but introduced more pipelining for speed enhancement. 80486 has five stages of pipelining. Two out of five stages are used for decoding complex instructions of 80486 architecture. The 80486 is also the first amongst the xxx86 processors to have an on-chip cache. This 8 Kbytes of cache is a unified data and code cache and acts on the physical addresses. Note: 80486 SX does not have floating point unit 32-bit address lines: (A 2 - A 31 , BE 0 - BE 3 ) 32-bit data lines: (D 0 - D 31 )